1. Field of the Invention
The present invention relates to a semiconductor integrated circuit having a plurality of types of voltage generators. The present invention also relates to a semiconductor integrated circuit having a plurality of operation modes.
2. Description of the Related Art
Recently, portable equipment which operates on batteries is becoming common. Semiconductor integrated circuits to be implemented in such portable equipment must be of low power consumption for the sake of extended use time of the batteries. This kind of semiconductor integrated circuit therefore contains a voltage generator for generating an internal power supply voltage lower in voltage than the external power supply voltage. The internal power supply voltage is supplied to internal circuits of the semiconductor integrated circuit to achieve low power consumption. In addition, such semiconductor integrated circuits as a DRAM have a voltage generator that generates a boosted voltage (internal power supply voltage) for word lines. That is, a plurality of types of internal power supply voltages generated by a plurality of types of voltage generators are supplied to a plurality of internal circuits, respectively.
Furthermore, in this kind of semiconductor integrated circuit, the voltage generators are made of a plurality of units having different capabilities. The units to be operated are switched in accordance with the operation mode, thereby achieving low power consumption. For example, in a DRAM, units of greater capabilities are operated in an active mode where read operations and write operations are performed (when word lines are selected). In a standby mode where no available command is supplied (when no word line is selected), units of smaller capabilities are operated. Moreover, in a power-down mode (low power consumption mode), operations of all the units are suspended and the generation of the internal power supply voltages is stopped. Here, latch circuits and the like that need to retain data are exclusively supplied with the external power supply voltage while the other circuits stop operating. The power consumption hence lowers further.
As described above, the generation of the internal power supply voltages is stopped in the power-down mode. Thus, when the semiconductor integrated circuit shifts its state from the standby mode or the active mode to the power-down mode, internal power supply lines for supplying the internal power supply voltages become floating. On this occasion, the charges trapped in the internal power supply lines are gradually drained out to a ground line through leak paths. That is, the internal power supply voltages drop gradually.
FIG. 1 shows variations of internal power supply voltages VPP and Vii (hereinafter, referred to as a boosted voltage VPP and a step-down voltage Vii) upon shifting from the standby mode to the power-down mode. Depending on the configuration of the leak paths, the boosted voltage VPP may drop earlier than the step-down voltage Vii so that the boosted voltage VPP falls below the step-down voltage Vii (FIG. 1(a)). Here, some circuits receiving the boosted voltage VPP and the step-down voltage Vii can cause a malfunction. Incidentally, the configuration of the leak paths depends on the substrate structure of the semiconductor integrated circuit, the circuit layout thereof, and so on.
FIG. 2 shows an example of the malfunction of a semiconductor integrated circuit. This example illustrates a malfunction occurring in CMOS inverters 2, 4 and a latch circuit 6 which are connected in cascades. The pMOS transistor of the CMOS inverter 2 is connected at its source to a boosted power supply line VPP. The pMOS transistor of the CMOS inverter 4 is connected at its source to a step-down power supply line Vii. The latch 6 has two CMOS inverters 8 whose inputs and outputs are connected to each other. The pMOS transistor of each CMOS inverter 8 is connected at its source to an external power supply line VDD.
In the standby mode, an input signal IN shall be logic 0, the output of the CMOS inverter 2 logic 1 (boosted voltage VPP), the output of the CMOS inverter 4 logic 0, and the output OUT of the latch circuit 6 logic 1. When the operation mode of the semiconductor integrated circuit shifts to the power-down mode and the boosted voltage VPP falls below the step-down voltage Vii as shown in FIG. 1(a), the input of the CMOS inverter 4 turns from logic 1 to logic 0. The CMOS inverter 4 outputs logic 1 incorrectly, thereby inverting the data of the latch circuit 6. In other words, the data of the latch circuit 6 to be retained during the power-down mode is corrupted. Consequently, the semiconductor integrated circuit can malfunction when it shifts from the power-down mode to the standby mode or the active mode.
It is an object of the present invention to prevent a semiconductor integrated circuit from malfunctioning. In particular, the object is to prevent internal circuits of a semiconductor integrated circuit which has a plurality of operation modes from malfunctioning upon switching between the operation modes.
According to one of the aspects of the semiconductor integrated circuit of the present invention, a first voltage generator generates a first internal power supply voltage to be supplied to a first internal power supply line. A second voltage generator generates a second internal power supply voltage to be supplied to a second internal power supply line. A short circuit shorts the first internal power supply line and the second internal power supply line when operations of both the first and second voltage generators are suspended.
For example, the first and second voltage generators generate the first and second internal power supply voltages based on an external power supply voltage, respectively. Besides, for example, the first internal power supply voltage is a boosted voltage higher than the external power supply voltage. The second internal power supply voltage is a step-down voltage lower than the external power supply voltage.
When the first and second voltage generators stop operating, the first and second internal power supply lines become floating. The charges stored in the respective internal power supply lines drain out gradually through leak paths. Here, since the charges are redistributed to both of the internal power supply lines, the first internal power supply voltage and the second internal power supply voltage become equal in value as they drop off.
Thus, for example, when the first internal power supply voltage is higher than the second internal power supply voltage, the first internal power supply voltage will never fall below the second internal power supply voltage after the first and second voltage generators stop operating. Consequently, the first and second internal power supply voltages can be prevented from inversion, and internal circuits connected to both the first and second internal power supply lines respectively can be precluded from malfunctioning.
According to another aspect of the semiconductor integrated circuit of the present invention, the short circuit includes a transistor having one of its source and drain connected to the first internal power supply line and having the other of the source and drain connected to the second internal power supply line. Consequently, the first and second internal power supply lines can be shorted to each other by a simple short circuit.
According to another aspect of the semiconductor integrated circuit of the present invention, a first internal circuit operates in response to receiving the first and second internal power supply voltages, respectively. The semiconductor integrated circuit has a power-down mode for suspending operations of the first and second voltage generators and for stopping the supply of the first and second internal power supply voltages to the first internal circuit. The transistor turns on in response to a power-down control signal indicating the power-down mode. Thus, the first and second internal power supply lines can be shorted quickly in synchronization with the shift to the power-down mode. In addition, the short circuit can be controlled by the simple logic circuit.
According to another aspect of the semiconductor integrated circuit of the present invention, the semiconductor integrated circuit has a power-down mode for suspending operations of the first and second voltage generators and for stopping the supply of the first and second internal power supply voltages to the first internal circuit. The first internal circuit is connected to both the first and second internal power supply lines. A second internal circuit is connected to an external power supply line. The second internal circuit operates in response to an output of the first internal circuit. That is, the second internal circuit receives the external power supply voltage directly, and hence operates even during the power-down mode. The short circuit shorts the first internal power supply line and the second internal power supply line during the power-down mode.
Upon shifting to the power-down mode, the first and second internal power supply voltages drop gradually. Here, since the short circuit shorts the first and second internal power supply lines to each other, the first and second internal power supply voltages are prevented from inversion. On this account, the first internal circuit outputs signals of correct logic without malfunctioning until the first and second internal power supply voltages fall to a predetermined voltage (a voltage which allows circuit operation).
Consequently, the second internal circuit which operates even during the power-down mode can be prevented from malfunctioning in response to an incorrect output from the first internal circuit. As a result, it is possible to prevent the semiconductor integrated circuit from malfunctioning after the release of the power-down mode.
According to another aspect of the semiconductor integrated circuit of the present invention, the semiconductor integrated circuit has a first operation mode and a second operation mode aside from the power-down mode. For example, the first operation mode is a standby mode in which the internal circuits are in a static state. The second operation mode is an active mode in which the internal circuits operate. The first voltage generator has a first voltage generating unit for operating during the first operation mode and a second voltage generating unit for operating during the second operation mode. The second voltage generator has a third voltage generating unit for operating during the first operation mode and a fourth voltage generating unit for operating during the second operation mode.
On the occasion when the semiconductor integrated circuit switches its state from the first operation mode or the second operation mode to the power-down mode, the first and third voltage generating units or the second and fourth voltage generating units stop operating. Then, the short circuit shorts the first and second internal power supply lines. Consequently, even when the semiconductor integrated circuit has the plurality of operation modes, malfunctioning of the internal circuits can be prevented by shorting the first and second internal power supply lines upon shifting to the power-down mode.
According to another aspect of the semiconductor integrated circuit of the present invention, the first voltage generator has a first detecting circuit for operating during the first operation mode to perform feedback control over the first voltage generating unit in accordance with the first internal power supply voltage. The first voltage generator also has a second detecting circuit for operating during the second operation mode to perform feedback control over the second voltage generating unit in accordance with the first internal power supply voltage. The second voltage generator has a third detecting circuit for operating during the first operation mode to perform feedback control over the third voltage generating unit in accordance with the second internal power supply voltage. The second voltage generator also has a fourth detecting circuit for operating during the second operation mode to perform feedback control over the fourth voltage generating unit in accordance with the second internal power supply voltage. Each of the detecting circuits stops its detecting operation during the power-down mode. This can prevent the detecting circuits from doing incorrect detecting operations when the first and second internal power supply lines are shorted and the first and second internal power supply voltages vary during the power-down mode.